This invention relates generally to PSK data detectors and particularly PSK data detectors utilized in television signal scrambling systems.
Phase locked loops (PLL) are well-known in the art. When such loops are utilized with phase shift keyed (PSK) binary data systems, they suffer an inherent drawback in that there is an unstable lock condition. One well-known system for detecting binary PSK data is known as a Costas loop, which in essence, comprises a pair of multipliers that are driven by an oscillator, with one multiplier driven in phase and the other driven in phase quadrature with respect to an incoming RF signal. Both multiplier outputs are supplied, through matched low pass filters to a third multiplier, that is used to make it bi-phase stable. The detected binary PSK data is taken from the in-phase input to the third multiplier. The output of the third multiplier is supplied through another low pass filter to the voltage controlled oscillator (VCO). The circuit is bi-phase stable with the third multiplier functioning to maintain the loop locked despite the carrier phase alterations due to the data. The Costas loop suffers the limitation of all PLL systems in terms of its very slow acquisition time. The Costas loop also suffers from a restricted frequency pull-in range.
U.S. Pat. No. 4,072,909 entitled AUTOMATIC PHASE AND FREQUENCY CONTROL SYSTEM issued Feb. 7, 1978 to R. Citta describes a loop that uses both phase and frequency locking. It is called an FPLL, and has the characteristics of both wide and rapid frequency acquisition and the desirable aspects of a phase locked loop system. It also is bi-phase stable. That arrangement utilized a third multiplier which is directly supplied from one of the phase quadrature multipliers, but supplied through a low pass filter and limiter (in a phase delay arrangement) from the other multiplier. The output of the third multiplier is supplied, through a low pass filter, to the input of the VCO. That system is characterized by a wide frequency acquisition range (even with very narrow PLL bandwidths). U.S. Pat. No. 4,091,410 entitled FREQUENCY AND PHASE LOCK LOOP SYNCHRONOUS DETECTlNG SYSTEM HAVING A PAIR OF PHASE LOCK CONDITIONS issued May 23, 1978 to R. Citta describes an FPLL circuit as above mentioned used as a video detector in a television receiver. ln that circuit, the phase ambiguity of the FPLL arrangement presented a serious problem that had to be overcome by special circuitry to assure that the video signal always had the same polarity. The arrangement used the output of the limiter, which is phase indicative of the input RF signal, to develop a phase inverting signal for maintaining a constant phase of video output signal.
The present invention retains the frequency acquisition range and phase locked stability of the FPLL of the above patents in addition to providing reliable binary PSK data detection. The novel arrangement presents an extremely attractive solution for low cost, high reliability television signal descrambling systems in which the video signal is scrambled by suppressing the horizontal syncs and inverting the phase of the carrier and data is transmitted by modulating the widths of the horizontal intervals. The wide frequency acquisition range and phase locked stability of the system of the invention obviates the need for precision crystal control of frequency and makes possible an economical, high reliability decoder for use in a CATV system. This is achieved in the FPLL of the invention by suitably tailoring the low pass filter bandwidths with respect to the data rate, that is the reciprocal of the time required to transmit each bit of information.